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a mastery course · one path · down the stack

Learn to make TPUs fast.

This page is the stack. Scroll and you descend it: four layers of compiler land on paper, the gap, then the shaded depths where kernels live. Each layer is a chapter with assigned mastery work; the stages are pinned where they belong; your progress rides on every entry.

3/6 gates passed · your progress 0/15 chapters

01 Read any IR on sight · narrate unfamiliar dumps, decode any dot_general
02 Write kernels that beat XLA · derived, differential-tested, benchmarked
03 Treat the cluster as one kernel · communication hidden behind compute
EX·03 streaming attention · a chapter 13 instrument, live
HBMQQKK0K1K2K3VV0V1V2V3VMEMqQ (resident)kAK0vAV0kBK1vBV1CARRIED STATEm : max(m, rowmax S1)l : l·e^(m₋−m) + rowsum e^(S1−m)acc : acc·e^(m₋−m) + e^(S1−m)·V1MXU · S = Q·K1ᵀ, then acc

03/06step 2 · one pass over K1, V1: rescale (m, l, acc), never materializing scores to HBM

scrub it: the carried (m, l, acc) state rescales exactly; the score matrix never exists
↓ the descent · nine layers · six stages pinned along the way
ch 01

JAX / PyTorch

Math on whole arrays. No notion of hardware.

ch 02

jaxpr

The traced program: a flat list of primitive ops.

ch 03

StableHLO

The portable tensor IR every framework lowers into.

ch 04

XLA

Fuses along dataflow edges. Cannot restructure an algorithm.

ch 05

the gap

XLA stops at fusion. Pallas asks for everything by hand. Between them: nothing. Stage 3 teaches you to cross on foot.

ch 06

Pallas

Hand choreography: BlockSpecs, grids, VMEM residency, DMA.

ch 07

Mosaic → LLO

The TPU backend. Kernels compile here; you never touch it.

ch 08

The machines

MXU, VPU, VMEM, HBM. Where all the time is actually spent; the GPU taught alongside, for contrast.

ch 09

ICI ⇄ chips

The inter-chip links. Collectives are kernels here too.

you have reached the floor

The workshop

Below the stack sits the equipment: twelve instruments, six gym stations, eight museum exhibits, fifteen labs. Every one is assigned to a chapter above; press ⌘K to jump anywhere.

the honesty rule

Gates pass only on real hardware, and failures stay published. Every value on this site states what it is: a roofline prediction, an off-chip verification, or a measured run with chip, dtype, shapes, and date attached.

measured on v6e-1 · the power rows · full provenance on the bench
pallas fused softmax, retuned222.7 µs vs 379.5 µs unfused, 267.6 µs XLA fused
windowed attention, mask as loop bound272.2 µs vs 1326.9 µs XLA masked (4.87x), 834.2 µs dense (3.06x)
flash vs naive, scaling curve1.05x at 4k, 1.22x at 8k, 1.23x at 16k, 1.35x at 32k; 4.15x vs reference at 32k