Reading the autotune cache

The chapter above taught the mechanism: candidates fingerprinted, duplicates collapsed, a timed race, a cached answer. Here is what the cache actually holds. The entry below is quoted verbatim from the XLAThe compiler: brilliant at fusing along dataflow edges, structurally unable to change your algorithm. That gap is why kernels exist.taught in /l/xla → repository's own test data, which makes it a real verdict from a real race, checked in by the people who run them.

version: 3
results {
  device: "CUDA: 8.0, Cores: 108, GPU clock: 1.41 GHz, Memory bandwidth: 1555 GB/s, L2 cache: 40 MB"
  hlo: "{\n  tmp_0 = f16[1,16,17,3]{3,2,1,0} parameter(0)\n  tmp_1 = f16[16,51]{1,0} bitcast(f16[1,16,17,3]{3,2,1,0} tmp_0)\n  tmp_2 = s8[16,17,3]{2,1,0} parameter(1)\n  tmp_3 = s8[51,16]{0,1} bitcast(s8[16,17,3]{2,1,0} tmp_2)\n  tmp_4 = f16[51,16]{0,1} convert(s8[51,16]{0,1} tmp_3)\n  tmp_5 = f16[16,16]{1,0} dot(f16[16,51]{1,0} tmp_1, f16[51,16]{0,1} tmp_4), lhs_contracting_dims={1}, rhs_contracting_dims={0}\n  ROOT tmp_6 = f16[1,16,16]{2,1,0} bitcast(f16[16,16]{1,0} tmp_5)\n}"
  result {
    run_time {
      nanos: 31744
    }
    triton {
      block_m: 32
      block_n: 32
      block_k: 32
      num_stages: 1
      num_warps: 4
      num_ctas: 1
    }
  }
}

The device string is the answer's address, and every clause narrows it: compute capability 8.0, 108 cores, 1.41 GHz, 1555 GB/s of memory bandwidth, 40 MB of L2. Those numbers name an A100, and they should be familiar: 108 is the SM count the GPU chip lesson tabulated for Ampere. The verdict is keyed to exactly this silicon, which is the reproducibility warning of the chapter made structural.

The hlo field is the fingerprint's subject: the fused computation printed whole, a dot with its bitcasts and an s8-to-f16 convert pulled in. Two instructions that print identically collapse to one race, and this text is what identical means.

And the result block is the race's outcome. The candidate space here is Triton tile configurations, and the winner is written out plainly: 32 by 32 by 32 blocks, one stage, four warps32 GPU threads scheduled as one unit; the GPU hides latency by switching among resident warps rather than by pipelining a scratchpad.taught in /l/tpu →, one CTA. Above it sits the number that decided everything: run_time of 31744 nanoseconds. Not a model's estimate. A stopwatch reading.

Read as a contract, the entry says: on this exact device, for this exact fused computation, this tile configuration won a timed race by the recorded margin. Change the chip generation or the driver and the address no longer matches, which is why autotuned answers do not travel and why the chapter prices reproducibility the way it does. The dumps-on-demand lesson's habit applies here unchanged: when a GPU program's performance shifts across environments, the autotune verdicts are part of the program's identity, and diffing them is as legitimate as diffing the HLO.